In conventional CMOS gate circuits used for semiconductor integrated circuits, when the rising transition of the output voltage signal of a front gate occurs, the wire capacitance and the input capacitance of a subsequent gate are charged so that the output voltage signal of the subsequent gate is fallen. Alternatively, when the falling transition of the output voltage signal of the front gate occurs, the wire capacitance and the input capacitance of the subsequent gate are discharged so that the output voltage signal of the subsequent gate is risen.
FIG. 1 is an inverter using the conventional CMOS transistor. In the inverter, a P-channel CMOS transistor 200 and a N-channel CMOS transistor 202 are complementarily connected. For example, when the output of a front inverter 204 falls to 0, the P-channel CMOS transistor 200 is turned on and the N-channel CMOS transistor 202 is turned off so that the output is transferred to 1. Alternatively, when the output of the front inverter 204 rises to 1, the P-channel CMOS transistor 200 is turned off and the N-channel CMOS transistor 202 is turned on so that the output is transferred to 0.
In such conventional inverter, the size of both of the P-channel CMOS transistor 200 and the N-channel CMOS transistor 202 are enlarged in order to speed up the falling transition and the rising transition of the output responsive to the rising transition and the falling transition, respectively.
Where, paying attention to the timing at which the P-channel CMOS transistor 200 is turned on and the N-channel CMOS transistor 202 is turned off as FIG. 2, since the voltage waveform passed through the P-channel CMOS transistor 200 which is turned on should be rapidly transferred, it is enlarged according to need. Meanwhile the N-channel CMOS transistor 202 might be downsized to facilitate to be turned off in this case.
However, in the conventional circuit, when the P-channel CMOS transistor 200 is turned off and the N-channel CMOS transistor 202 is turned on in the subsequent reversed phase output transition, the voltage waveform also should be rapidly transferred so that the transistor size is normally designed as P/N=2 in order to enable the high-speed transition at both of the rising and the falling of the output. Therefore, in the conventional CMOS circuit, the transistor turned off can not be downsized because it will be turned on at the next process nevertheless the size of the transistor turned off is enough to be smaller. Thus the unnecessary capacitance is included because of the above described large size so that the passing delay is increased thereby the high-speed transmission is prevented. Where the passing delay Tpd of the gate is essentially expressed by the following formula.
                              T          pd                =                              C            ·            V                    I                                    (        1        )            
(where, C is capacitance, V is voltage, and I is on-state current of the transistor) According to the formula, the passing delay Tpd of the gate can be reduced by decreasing the capacitance C or the voltage V, or increasing the on-state current I. The capacitance C includes a parasitic capacitance such as a gate capacitance and a junction capacitance in the CMOS transistor's own, and a load capacitance such as a wiring. The parasitic capacitance in the transistor's own is increased in proportion as the transistor size thereby the high-speed transmission is prevented.